The present invention relates to design technology of a semiconductor integrated circuit device and particularly, to technology effective for optimization processing of layout processing in a semiconductor integrated circuit device.
As layout design technology of a semiconductor integrated circuit device, for example, the use of an automatic layout design tool for automatically designing a layout, that is, a so-called electronic design automation (EDA) tool is widely known.
Upon receipt of coupling information (net list=logic circuit design result) of cells or macro cells, the automatic layout design tool automatically determines the positions of cells or macro cells over a semiconductor chip and places them and performs processing to automatically couple them etc.
As optimization technology of cell layout using this kind of EDA tool, for example, that which, as shown in FIG. 19, does not take into consideration the timing in an initial layout but improves the layout position or changes the floor plan based on the timing optimization result after the layout, or that which, as shown in FIG. 20, calculates timing in an initial state, places a critical timing path in the initial state in proximity and after optimization, changes the floor plan etc. if the timing does not converge, is known.
In the optimization technology of the cell layout shown in FIG. 19 and FIG. 20, a circuit to be given is a circuit (shown on the left side in FIG. 21 and on the left side in FIG. 22, respectively) configured by flip-flops and paths. Here, the path indicates a signal path configured by combined circuits. Elements configuring the flip-flop and the combined circuit are referred to as cells.
Optimization of cell layout is to determine cell positions so that wiring is possible with the minimum wiring length and a timing constraint given between flip-flops connected by a path in the timing optimization in the next step can be met.